Date of Award

12-1-1999

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Computer Science

First Advisor

Dr. Hesham H. Ali

Abstract

As our reliance on electric and electronic devices increases, the need to improve the design and manufacture of integrated circuits (ICs) grows. A microchip can be bettered if it can be made more powerful, smaller, cheaper, and/or more easily manufactured. The physical design phase of chip manufacture offers significant room for improvement. This thesis intends to investigate the detailed channel routing phase of VLSI physical design. Channel routing has been seen to be intractable, in that an optimal solution may require too much time for calculation. Constraints severely limit many algorithms to an approximate solution. The heuristics developed thus far have fallen short of an optimal solution for similar reasons. This thesis presents an evolutionary approach to channel routing. A genetic algorithm makes use of a parent solution to derive next generation solutions in an attempt to overcome local minimums. A three-layer approach is used to evaluate the use of various layering schemes, and also to reduce the number of constraints involved. When multi-terminal nets or multi-nets are involved, a division parameter is used to determine if the best results are generated by treating the multi-net as a whole, or broken down into as small as two-terminal nets. A greedy approach is used to generate the original parents, and a compaction algorithm is used to further improve the output. The results are then represented three-dimensionally by a computer-aided design program, where it can be analyzed for accuracy.

Comments

A Thesis Presented to the Department of Computer Science and the Faculty of the Graduate College University of Nebraska In Partial Fulfillment of the Requirements for the Degree Master of Science University of Nebraska at Omaha. Copyright 1999 Mark P. Cloyed

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